1. Technical Field
The invention relates generally to integrated circuits formed using trench structures, and more specifically, to shallow trench capacitor structures.
2. Background Art
As more circuits are packed onto a given semiconductor substrate, more thought has been devoted to not only orienting the various devices in a planar fashion along the surface of the substrate, but to orienting the devices vertically by either building the devices up from the substrate surface or by burying the devices in trenches formed within the face of the semiconductor body. Some examples of trench structures include trench capacitors, which have been used in dynamic random access memory (DRAM) cells and other circuits to try and further reduce the overall area of the cell. Examples of trench capacitors are found in the following U.S. patents: U.S. Pat. No. 4,694,561, "Method of Making High-Performance Trench Capacitors for DRAM Cells", issued September 1987 to Lebowitz; U.S. Pat. No. 4,859,615, "Semiconductor Memory Cell Capacitor and Method for Making the Same", issued August 1989 to Tsukamoto et al.; U.S. Pat. No. 4,889,492, "High Capacitance Trench Capacitor and Well Extension Process", issued December 1989 to Barden et al.; and U.S. Pat. No. 5,466,628, "Method of Manufacturing Trench Capacitor With a Recessed Field Oxide Layer", issued November 1995 to Lee et al.
There are several problems, though, with fabricating a capacitor used for high density DRAMS and logic technologies, such as for decoupling or storage. One problem is the fabrication area required of this capacitor makes it undesirable to use the planar silicon area. Hence, a deep trench has been used in fabricating capacitors with minimal area. However, a second problem ensues with using a deep trench capacitor in high density DRAMS and logic technologies- the dielectric of the deep trench capacitor cannot reliably withstand maximum operating voltage conditions.